? semiconductor components industries, llc, 2011 october, 2011 ? rev. 3 1 publication order number: PACVGA105/d PACVGA105 vga port companion circuit product description the PACVGA105 incorporates 7 channels of esd protection for signal lines commonly found in a vga port for pcs. esd protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the iec ? 1000 ? 4 ? 2 level ? 4 esd protection standard ( ? 8 kv contact discharge). when the channels are subjected to an electrostatic discharge, the esd current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. the upper esd diodes for the r, g and b channels are connected to a separate supply rail (v rgb ) to facilitate interfacing to graphics controller ics with low voltage supplies. the remaining channels are connected to the main 5 v rail (v cc ). the lower diodes for the r, g and b channels are also connected to a dedicated ground pin (gnda) to minimize crosstalk due to common ground impedance. two non ? inverting buffers are also included in this ic for buffering the hsync and vsync signals from the graphics controller ic. these buf fers will accept ttl input levels and convert them to cmos output levels that swing between gnd and v cc . these drivers have a nominal 60 output impedance to match the characteristic impedance of the hsync and vsync lines of the video cables typically used. the inputs of these drivers also have high impedance pull ? ups (50 k nom.) pulling up to the v aux rail. in addition, the ddc_clock and ddc_data channels have 1.8 k resistors pulling these inputs up to the main 5 v (v cc ) rail. features ? seven channels of esd protection designed to meet iec ? 1000 ? 4 ? 2 level ? 4 esd requirements ( ? 8 kv contact discharge) ? very low loading capacitance from esd protection diodes at less than 5 pf typical ? ttl to cmos level ? translating buffers for the hsync and vsync lines ? three independent supply pins (v cc , v rgb and v aux ) to facilitate operation with sub ? micron graphics controller ics ? high impedance pull ? ups (50 k nominal to v aux ) for hsync and vsync inputs ? pull ? up resistors (1.8 k nominal to v cc ) for ddc_clk and ddc_data lines ? compact 16 ? pin qsop package ? these devices are pb ? free and are rohs compliant applications ? esd protection and termination resistors for vga (video) port interfaces ? desktop pcs ? notebook computers ? lcd monitors http://onsemi.com marking diagram device package shipping ? ordering information PACVGA105qr qsop16 (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. qsop16 qr suffix case 492 PACVGA105qr = specific device code yy = year ww = work week g = pb ? free package pacvga 105qr yywwg
PACVGA105 http://onsemi.com 2 simplified electrical schematic gnda b g r v rgb hsync vsync ddc_data ddc_clk v cc v aux vsync_out hsync_out 50 k 50 k 1.8 k 1.8 k gndd package / pinout diagrams 16 ? pin qsop hsync_out 1 2 3 9 16 top view v cc 4 5 6 7 8 10 11 12 13 15 14 hsync gndd v rgb b g r gnda vsync_out vsync v aux ddc_clk gndd v cc ddc_data table 1. pin descriptions lead(s) name description 1 hsync_out horizontal sync signal buffer output. connects to the video connector side of the horizontal sync line. 2 hsync horizontal sync signal buffer input. connects to the vga controller side of the horizontal sync line. 3, 11 gndd digital ground reference supply pin. 4 v rgb v rgb supply pin. this is an isolated supply pin for the r, g and b esd protection circuits. 5 b blue signal video protection channel. this pin is typically tied to the b video line between the vga controller device and the video connector. 6 g green signal video protection channel. this pin is typically tied to the g video line between the vga controller device and the video connector. 7 r red signal video protection channel. this pin is typically tied to the r video line between the vga controller device and the video connector. 8 gnda analog ground reference supply pin. 9, 16 v cc v cc supply pin. this is the main supply input for the ddc_clk and ddc_data pullup resistors and esd protection circuits. it is also connected to the sync buffers and to the esd protection diodes present on the hsync_out and vsync_out lines. 10 ddc_data ddc data pin. 12 ddc_clk ddc clock pin. 13 v aux v aux supply pin. this is the supply input for the 50 k pullups connected to the hsync and vsync buffer inputs. 14 vsync vertical sync signal buffer input. connects to the vga controller side of the vertical sync line. 15 vsync_out vertical sync signal buffer output. connects to the video connector side of the vertical sync line.
PACVGA105 http://onsemi.com 3 specifications table 2. absolute maximum ratings parameter rating units v cc , v rgb , v aux supply voltage inputs [gnd ? 0.5] to +6.0 v diode forward current (one diode conducting at a time) 20 ma dc voltage at inputs r, g, b hsync, vsync ddc_clk, ddc_data [gnd ? 0.5] to [v rgb + 0.5] [gnd ? 0.5] to [v aux + 0.5] [gnd ? 0.5] to [v cc + 0.5] v operating temperature range 0 to +70 ? c storage temperature range ? 40 to +150 ? c package power rating 750 mw stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 3. standard operating conditions symbol parameter min max units v cc main supply voltage 4.5 5.5 v v rgb rgb supply voltage 1.7 3.7 v v aux auxiliary supply voltage 2.9 3.7 v v ih logic high input voltage (note 1) 2.0 v v il logic low input voltage (note 1) 0.8 v v i input voltage rgb hsync, vsync ddc_clk, ddc_data 0 0 0 v rgb v aux v cc v i oh high level output current (note 1) ? 8 ma i ol low level output current (note 1) 8 ma t a free ? air operating temperature 0 +70 ? c 1. these parameters apply only to the hsync and vsync signals.
PACVGA105 http://onsemi.com 4 specifications (cont?d) table 4. electrical operating characteristics (note 1) symbol parameter conditions min typ max units v f diode forward voltage i f = 10 ma 1.0 v v oh logic high output voltage i oh = ? 4 ma, v cc = 4.5 v 4.0 v v ol logic low output voltage i ol = 4 ma, v cc = 4.5 v 0.4 v i in input current r, g and b pins hsync, vsync pins hsync, vsync pins v rgb = 3.63 v, v in = v rgb or gnd v aux = 3.63 v, v in = v aux v aux = 3.63 v, v in = gnd ? 30.0 ? 72.5 ? 1 ? 1 ? 95.0 a i cc v cc supply current v cc = 5.5 v, v aux = v rgb = 2.97 v, all inputs and outputs floating 35 100 a i rgb v rgb supply current r, g and b pins at v cc or gnd, all inputs and outputs floating 10 a c in input capacitance r, g and b pins hsync, vsync pins ddc_data, ddc_clk pins note 2 applies for all cases 5 10 5 pf r pu pull ? up resistance ddc_data, ddc_clk pins 1.62 1.80 1.98 k v esd esd withstand voltage v cc = 5 v, v rgb = 3.3 v, v aux = 3.3 v (note 3) ? 8 kv t plh sync buffer l ? h propagation delay c l = 50 pf, v cc = 5.0 v, r l = 500 (note 4) 7.0 15.0 ns t phl sync buffer h ? l propagation delay c l = 50 pf, v cc = 5.0 v, r l = 500 (note 4) 7.0 15.0 ns t r, t f sync buffer output rise & fall times c l = 50 pf, v cc = 5.0 v, r l = 500 (note 4) 7.0 ns 1. all parameters specified over standard operating conditions unless otherwise noted. 2. measured at 1 mhz. r/g/b inputs biased at 1.65 v with v rgb = 3.3 v. ddc_clk and ddc_data biased at 2.5 v with v cc = 5 v. hsync and vsync inputs biased at v aux or gnd with v aux = 3.3 v and v cc = 5 v. 3. per the iec ? 61000 ? 4 ? 2 international esd standard, level 4 contact discharge method. v rgb and v cc must be bypassed to gnd via a low impedance ground plane with a 0.2 f, low inductance, chip ceramic capacitor at each supply pin. esd pulse is applied between the applicable pins and gnd. esd pulse can be positive or negative with respect to gnd. applicable pins are: r, g, b, hsync_out, vsync_out, ddc_clk and ddc_data. the hsync and vsync inputs are esd protected to the industry standard 2 kv per the human body model (mil ? std ? 883, method 3015). 4. applicable to the sync buffers only. input signals swing between 0 v and 3.0 v, with rise and fall times ? 5 ns. guaranteed by correlation to buffer output drive currents.
PACVGA105 http://onsemi.com 5 application information figure 1. typical connection diagram 2 digital gnd h ? sync video controller v ? sync ddc_data ddc_clk red green blue h ? sync v ? sync ddc_data ddc_clk red green blue ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? video connector hsync vsync ddc_data ddc_clk r g b analog gnd hsync_out vsync_out gnda gndd PACVGA105 14 10 12 7 6 5 4 9, 16 13 8 3, 11 1 15 to video dac v dd 5 v 3.3 v 0.2 f 0.2 f sf** vf** sf** vf** vf** vf** ? video emi filter sf** ? sync emi filter v rgb v cc v aux gnda, the negative voltage rail for the r, g and b diodes is not connected internally to gndd. gnda should ideally be connected to the ground of the video dac ic. this will prevent any ground bounce caused by digital signals from injecting noise onto the r, g and b signals. analog gnd and digital gnd are typically connected on the printed circuit board.
PACVGA105 http://onsemi.com 6 package dimensions qsop16 case 492 ? 01 issue a e m 0.25 c a1 a2 c detail a detail a h x 45 dim max min inches a 0.053 0.069 b 0.008 0.012 l 0.016 0.050 e 0.025 bsc h 0.009 0.020 c 0.007 0.010 a1 0.004 0.010 m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. 4. dimension d does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.005 per side. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.005 per side. d and e1 are determined at datum h. 5. datums a and b are determined at datum h. b l 6.40 16x 0.42 16x 1.12 0.635 dimensions: millimeters 16 pitch soldering footprint 9 18 d d 16x seating plane 0.10 c e1 a a-b d 0.20 c e 18 16 9 16x c m d 0.193 bsc e 0.237 bsc e1 0.154 bsc l2 0.010 bsc d 0.25 c d b 0.20 c d 2x 2x 2x 10 tips 0.10 c h gauge plane c a2 0.049 ---- 1.35 1.75 0.20 0.30 0.40 1.27 0.635 bsc 0.22 0.50 0.19 0.25 0.10 0.25 0 8 4.89 bsc 6.00 bsc 3.90 bsc 0.25 bsc 1.24 ---- max min millimeters l2 a seating plane on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 PACVGA105/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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